Many computer devices operate based on an external clock. For example, a processor may receive a clock input and perform all operations or events only when the clock transitions. Devices in which events proceed based on a clock transition are referred to as “synchronous” devices.
Other computer devices do not base their operation on an external clock. These devices are referred to as “asynchronous” or “self-timed” devices. A self-timed device typically receives a request from a processor. The device then performs the operation and indicates to the processor when the operation is complete. However, the time required for the operation to complete is not based on an external clock (i.e., a predetermined number of clock cycles). Rather, in the case of a self-timed device, the time required is based on the asynchronous delay paths through the device, which may vary in duration based on the operations that are performed.
In a conventional memory controller architecture, the memory controller architecture generally includes a processor, a chipset and a main memory. A host system bus which connects the processor to the chipset is a synchronous device generally controlled by a common clock interface. In other words, the speed at which the host system bus can run is limited by the speed of the system clock. As technology pushes the processing speed, common clock interface buses run the risk of creating a bottleneck in memory controller architectures. In fact, these advances in processor design have pushed memory controller systems to a level where the speed of a bus or an architecture cannot be scaled using an increased clock frequency. One technique for accommodating the increased processor speed is to replace the host system bus with a source synchronous system bus.